1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and, more particularly, to a semiconductor integrated circuit with low power consumption.
2. Description of the Related Art
Portable electronic devices are different from general electronic devices because they are driven by a battery. Thus, it is important to reduce power consumption in the portable electronic device. In a large scale integrated circuit (LSI) chip employed in the portable electronic device, the power consumption is one of the important design factors. The power consumption problem with the portable electronic device which employs the LSI chip generally has two classifications.
One is the power consumption which occurs in an active state of the LSI chip, and the other is the power consumption that occurs in a standby state. For example, in case of a personal digital assistant (PDA), its LSI chip stays in the active state when a user continuously inputs data or executes a certain application program. However, when there is no data input or no execution of the application program during a certain time period, the LSI chip enters the standby state in which only internal requisite data necessary for returning to a normal operation are kept.
In the standby state, a clock necessary for the operation of the LSI chip turns off, and only a power voltage VDD is applied. Thus, hardware and software is designed such that even in the standby state the internal state of the LSI chip and stored data are maintained until the LSI chip returns to an active state.
In the case of the portable electronic device, standby time is generally longer than operation time. Thus, it is important to reduce the power consumption in the standby state. For the foregoing reason, LSI chips are being developed to provide various standby modes and minimize electric currents in the standby state.
In order to maintain data in the standby state, the LSI chip for the portable electronic device can be implemented with static logic. When the portable electronic device is designed with static logic, most of the power consumption is caused from leakage currents, such as a leakage current between the power voltage and the ground voltage, a leakage current in the PN junctions, and the like. Conventional methods for reducing the power consumption and improving the performance of the LSI chip have depended on a scaling down technique. That is, as a device is scaled down, the performance is improved by the shorter channel of a MOS transistor and the corresponding reduced capacitance. This, in turn, leads to lower power consumption and reduced operation voltage.
However, if a device is scaled down past a predetermined level, the operation speed can be significantly lowered due to an increase in the threshold voltage of a transistor. Therefore, in order to solve the problem, the threshold voltage of the transistor needs to also be lowered. However, if the threshold voltage of the transistor is low, the transistor may not be completely turned off in an off state resulting in a large amount of leakage current.
In order to solve the problem, a multi-threshold CMOS (MTCMOS) technique has been suggested.
FIG. 1 is a circuit diagram illustrating a conventional semiconductor integrated circuit.
The semiconductor integrated circuit of FIG. 1 includes a transistor having a low threshold and a transistor having a high threshold voltage. Transistors which constitute a logic circuit portion 10 are transistors having a low threshold voltage, and a transistor having a higher threshold voltage than the transistors of the logic circuit portion 10 is an NMOS transistor NM1.
One end of the NMOS transistor NM1 is connected to a ground voltage VSS, the other end is connected to a virtual ground V-GND, and a gate is connected to an active signal ACT. The logic circuit portion 10 which comprises the transistors having a low threshold voltage is arranged between a power voltage VDD and the virtual ground V-GND.
When the active signal ACT having a high level is applied in the active state of the MTCMOS circuit, the NMOS transistor NM1 having a high threshold voltage is turned on, and the virtual ground V-GND functions as an actual ground voltage and the resistance of the circuit is reduced.
On the other hand, when the active signal ACT has a low level in the standby state, the NMOS transistor NM1 is turned off, and the virtual ground V-GND is floated so that the ground voltage is blocked, which prevents leakage current from flowing.
That is, the MTCMOS turns on the NMOS transistor NM1 having a high threshold voltage to allow the electric current to flow before the logic circuit portion 10 enters the active state and turns off the NMOS transistor NM1 to block the leakage current when the logic circuit portion 10 enters the standby state.
The conventional semiconductor integrated circuit described above reduces the power consumption in the standby state, but since the MOS transistor having a high threshold voltage is used as a switch for controlling the power, when the NMOS transistor NM1 is turned on, the virtual ground V-GND and the ground voltage VSS are momentarily connected, which creates noise such as ground bounce noise in the supplied electric current, which may inhibit smooth transitional operation.